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Honored Contributor
Honored ContributorTimeQuest Timing Analyzer[Setup slack analysis]
HI, I am trying to understand how the Time Quest analyzer calculating required setup and hold time.I have written code for register and the clocks are common(50 MHz). As per my understanding da...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I'm not sure we're talking about the same thing.. What I'm saying is that, at the lowest level you have a circuit you can call a flip-flop, you can have negative Tsu or negative Th. In Altera terms, that's having a negative uTsu or a negative uTh. And not only you can have, but having negative Th is the prevalent type of flip-flop in integrated circuits nowadays. So, there's no sense in a convention that (u)Tsu and (u)Th are always positive. That convention falls apart in the face of actual, existing, circuits. --- Quote End --- The central theme in register timing is that a register(at its port level) needs input not to change before its clock edge (by +tSU time) and not to change after clock edge (by +tH time). So they must be positive. They only get negative relative to clock edge if you move your definition forwards say to clock/data pins.
