TimeQuest Timing Analyzer[Setup slack analysis]

The flop is a two state sampling device. By law of nature a sampling device needs to recognise its input state during a finite sampling window. If the input state is neither low nor high for a finite time then sampling naturally fails. That is the whole point. The second issue is how to measure this sampling window relative to what.

FPGAs view it at lowest level at flop ports before any further delays are inserted. It is possible that some fpgas may be produced with its internal intrinsic delays and hence the reference point changes. But the central physical theme stays regarding sampling a stable input.