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Honored Contributor
Honored ContributorTimeQuest Timing Analyzer[Setup slack analysis]
HI, I am trying to understand how the Time Quest analyzer calculating required setup and hold time.I have written code for register and the clocks are common(50 MHz). As per my understanding da...
Altera_ForumHonored Contributor
Honored ContributorHmm, that said... I'm not sure TQ was saying uTsu was positive in one place and negative in another place.
The OP made it look like that but... the only place where I see Tsu in TQ is in the "data required report". All the values there are, by convention, positive when they increase the "Data required" timing. I.e., positive uTsu show up as negative increments and negative uTsu as positive increments. I haven't bothered to fire up Vivado yet, as none of my current projects is going with a 7 series. Xilinx's doc has always been pretty good. Their software on the other hand, has induced several fits of homicidal rage. I do hope Vivado improves things.
