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IDeyn's avatar
IDeyn
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7 years ago

TimeQuest strange behavior - seems like a bug in PLL output clock visualization

Hi all! Recently faced such problem - in the test project there are two PLLs, with input from two base input clocks. One clock is 50 MHz with waveform { 0.000 10.000 } and on also 50 MHz with wavef...
IDeyn's avatar
IDeyn
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6 years ago

Hi Abe ,

Thank you very much for your answer.

It can be a real design case, where clocks are shifted on board, so we need a way to describe it in TQ.

So, again it looks that derive_pll_clocks can't be used with input clocks with phase shift, in that case we need to manually write generated_clocks, which is inconvenient.

In my opinion, it is a bug and it will be good if it will be corrected.

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Best regards,

Ivan