Timequest reports inverted SDRAM clock as shifted + 180 degrees

Your clocks were originally edge aligned, so when inverting the source clock, it makes sense that the setup requirement would get tighter(the most restrictive edges are always the defaults). You need to add a multicycle to say you're sending data out another period(which loosens the setup requirement, but makes the hold requirement more restrictive).

set_multicycle_path -setup -from [get_clocks CLK_OUT_120] -to [get_clocks pll_clk_120] 2

THe analysis should have a 12.499ns setup requirement and a 4.166ns hold requirement, I believe.

Thanks Rysc. With inverted 120 MHz clock in the design, using the -invert option on the create_generated_clock SDC statement as well as using a multicycle exception all TimeQuest violations are gone. Can you please review the below results and let me know if anything looks somehow suspicious? Thanks.

*************************

********* SDC ***********

*************************

# **************************************************************

# Time Information

# **************************************************************

set_time_format -unit ns -decimal_places 3

# **************************************************************

# Create Clock

# **************************************************************

create_clock -name CLK_IN_48 -period 20.833 -waveform { 0.000 10.416 } [get_ports CLK_IN_48]

# **************************************************************

# Create Generated Clock

# **************************************************************

create_generated_clock -name pll_clk_120 -source [get_pins inst|altpll_component|pll|inclk[0]] -duty_cycle 50.000 -multiply_by 5 -divide_by 2 -master_clock CLK_IN_48 [get_pins inst|altpll_component|pll|clk[2]] -add

create_generated_clock -name CLK_OUT_120 -source [get_pins inst|altpll_component|pll|clk[2]] -invert [get_ports sdram_clk]

# **************************************************************

# Set Output Delay

# **************************************************************

# SDRAM

set_output_delay -max -clock [get_clocks CLK_OUT_120] 1.5 [get_ports {sa[*], ba[*], cke, n_ras, n_cas, n_we, dq[*]}]

set_output_delay -min -clock [get_clocks CLK_OUT_120] -0.8 [get_ports {sa[*], ba[*], cke, n_ras, n_cas, n_we, dq[*]}]

# **************************************************************

# Set Input Delay

# **************************************************************

# SDRAM

set_input_delay -max -clock [get_clocks CLK_OUT_120] 5.4 [get_ports dq[*]]

set_input_delay -min -clock [get_clocks CLK_OUT_120] 3.0 [get_ports dq[*]]

# **************************************************************

# Set Multicycle Path

# **************************************************************

set_multicycle_path -setup -from [get_clocks CLK_OUT_120] -to [get_clocks pll_clk_120] 2

**********************************************

********* Previously failed path (now ok) ***********

**********************************************

report_timing -from_clock {CLK_OUT_120} -from [get_ports {dq[3]}] -setup -npaths 1 -detail path_only

Info: Path# 1: Setup slack is 1.750

Info: ===================================================================

Info: From Node : dq[3]

Info: To Node : SdramFifo:inst3|sdr_sdram:inst5|DQIN[3]

Info: Launch Clock : CLK_OUT_120

Info: Latch Clock : pll_clk_120

Info: Multicycle - Setup End : 2

Info:

Info: Data Arrival Path:

Info:

Info: Total (ns) Incr (ns) Type Element

Info: ========== ========= == ==== ===================================

Info: 4.166 4.166 launch edge time

Info: 7.318 3.152 R clock network delay

Info: 12.718 5.400 R iExt dq[3]

Info: 13.661 0.943 RR CELL dq[3]|combout

Info: 14.790 1.129 RR IC inst3|inst5|DQIN[3]~feeder|datad

Info: 14.968 0.178 RR CELL inst3|inst5|DQIN[3]~feeder|combout

Info: 14.968 0.000 RR IC inst3|inst5|DQIN[3]|datain

Info: 15.064 0.096 RR CELL SdramFifo:inst3|sdr_sdram:inst5|DQIN[3]

Info:

Info: Data Required Path:

Info:

Info: Total (ns) Incr (ns) Type Element

Info: ========== ========= == ==== ===================================

Info: 16.666 16.666 latch edge time

Info: 16.776 0.110 R clock network delay

Info: 16.814 0.038 uTsu SdramFifo:inst3|sdr_sdram:inst5|DQIN[3]

Info:

Info: Data Arrival Time : 15.064

Info: Data Required Time : 16.814

Info: Slack : 1.750

Info: ===================================================================

Info:

Looks good to me. I would also do a report_timing -hold on that path, just to make sure that is correct, as you should have a positive hold requirement.

I personally use derive_pll_clocks instead of explicitly constraining them. Yes you lose the ability to name the clock and instead get the ugly, long name, but I've seen enough projects get messed up because the .sdc didn't match the design, that it's my general recommendation, but it's really a matter of choice.

As for the -invert, you need to analyze yourself if TQ correctly picks that up. Feeding the actual registers, TQ can identify simple inversions, but when sending a clock out it gets more complicated. For example, I've sent a clock out using a DDR structure, where I tie the high register to ground and the low register to VCC. TQ doesn't recognize this as an inversion, and I have to add a -invert. It sounds like just a simple inversion won't be noticed on the clock line, so what you've done is correct.

Thanks Rysc. All timings are met in all timing models. I don't use derive_pll_clocks because i'm the only designer and i like to keep the SDC clean. I did someresearch and TimeQuest didn't pick up the inverted clock signal simply because the -source was set to the PLL output and not to the NOT gate output. It was easier to simply use the -invert SDC option than to dig out the NOT gate output from the net list and use it as -source.

Thank you (and others) for your help. All I/Os have now been constrained in my design and i've learned a lot about TimeQuest the last few weeks. I now just have to debug my design to find out why it no longer works ;)

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Thanks Rysc. All timings are met in all timing models. I don't use derive_pll_clocks because i'm the only designer and i like to keep the SDC clean. I did someresearch and TimeQuest didn't pick up the inverted clock signal simply because the -source was set to the PLL output and not to the NOT gate output. It was easier to simply use the -invert SDC option than to dig out the NOT gate output from the net list and use it as -source.

Thank you (and others) for your help. All I/Os have now been constrained in my design and i've learned a lot about TimeQuest the last few weeks. I now just have to debug my design to find out why it no longer works ;)

--- Quote End ---

Dear JohnG300C, I know this thread is very old. Can you please tell me the way you calculate 5.4ns for set_input_delay? I can not draw similar value when targeting an SDRAM. Thank you very much!