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Altera_Forum's avatar
Altera_Forum
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17 years ago

Timequest reports inverted SDRAM clock as shifted + 180 degrees

I need to move my SDRAM clock forward (positive phase shift) using an inverter and LCELLs to meet tsu of my Cyclone II inputs. My clock is 120 MHz and i have no more available PLL outputs to do the c...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Your clocks were originally edge aligned, so when inverting the source clock, it makes sense that the setup requirement would get tighter(the most restrictive edges are always the defaults). You need to add a multicycle to say you're sending data out another period(which loosens the setup requirement, but makes the hold requirement more restrictive).

set_multicycle_path -setup -from [get_clocks CLK_OUT_120] -to [get_clocks pll_clk_120] 2

THe analysis should have a 12.499ns setup requirement and a 4.166ns hold requirement, I believe.