Honored Contributor
Honored ContributorThanks Rysc. With inverted 120 MHz clock in the design, using the -invert option on the create_generated_clock SDC statement as well as using a multicycle exception all TimeQuest violations are gone. Can you please review the below results and let me know if anything looks somehow suspicious? Thanks.
************************* ********* SDC *********** ************************* # ************************************************************** # Time Information # ************************************************************** set_time_format -unit ns -decimal_places 3 # ************************************************************** # Create Clock # ************************************************************** create_clock -name CLK_IN_48 -period 20.833 -waveform { 0.000 10.416 } [get_ports CLK_IN_48] # ************************************************************** # Create Generated Clock # ************************************************************** create_generated_clock -name pll_clk_120 -source [get_pins inst|altpll_component|pll|inclk[0]] -duty_cycle 50.000 -multiply_by 5 -divide_by 2 -master_clock CLK_IN_48 [get_pins inst|altpll_component|pll|clk[2]] -add create_generated_clock -name CLK_OUT_120 -source [get_pins inst|altpll_component|pll|clk[2]] -invert [get_ports sdram_clk] # ************************************************************** # Set Output Delay # ************************************************************** # SDRAM set_output_delay -max -clock [get_clocks CLK_OUT_120] 1.5 [get_ports {sa[*], ba[*], cke, n_ras, n_cas, n_we, dq[*]}] set_output_delay -min -clock [get_clocks CLK_OUT_120] -0.8 [get_ports {sa[*], ba[*], cke, n_ras, n_cas, n_we, dq[*]}] # ************************************************************** # Set Input Delay # ************************************************************** # SDRAM set_input_delay -max -clock [get_clocks CLK_OUT_120] 5.4 [get_ports dq[*]] set_input_delay -min -clock [get_clocks CLK_OUT_120] 3.0 [get_ports dq[*]] # ************************************************************** # Set Multicycle Path # ************************************************************** set_multicycle_path -setup -from [get_clocks CLK_OUT_120] -to [get_clocks pll_clk_120] 2 ********************************************** ********* Previously failed path (now ok) *********** ********************************************** report_timing -from_clock {CLK_OUT_120} -from [get_ports {dq[3]}] -setup -npaths 1 -detail path_only Info: Path# 1: Setup slack is 1.750 Info: =================================================================== Info: From Node : dq[3] Info: To Node : SdramFifo:inst3|sdr_sdram:inst5|DQIN[3] Info: Launch Clock : CLK_OUT_120 Info: Latch Clock : pll_clk_120 Info: Multicycle - Setup End : 2 Info: Info: Data Arrival Path: Info: Info: Total (ns) Incr (ns) Type Element Info: ========== ========= == ==== =================================== Info: 4.166 4.166 launch edge time Info: 7.318 3.152 R clock network delay Info: 12.718 5.400 R iExt dq[3] Info: 13.661 0.943 RR CELL dq[3]|combout Info: 14.790 1.129 RR IC inst3|inst5|DQIN[3]~feeder|datad Info: 14.968 0.178 RR CELL inst3|inst5|DQIN[3]~feeder|combout Info: 14.968 0.000 RR IC inst3|inst5|DQIN[3]|datain Info: 15.064 0.096 RR CELL SdramFifo:inst3|sdr_sdram:inst5|DQIN[3] Info: Info: Data Required Path: Info: Info: Total (ns) Incr (ns) Type Element Info: ========== ========= == ==== =================================== Info: 16.666 16.666 latch edge time Info: 16.776 0.110 R clock network delay Info: 16.814 0.038 uTsu SdramFifo:inst3|sdr_sdram:inst5|DQIN[3] Info: Info: Data Arrival Time : 15.064 Info: Data Required Time : 16.814 Info: Slack : 1.750 Info: =================================================================== Info:
