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Altera_Forum
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17 years ago

Timequest reports inverted SDRAM clock as shifted + 180 degrees

I need to move my SDRAM clock forward (positive phase shift) using an inverter and LCELLs to meet tsu of my Cyclone II inputs. My clock is 120 MHz and i have no more available PLL outputs to do the c...
Altera_Forum's avatar
Altera_Forum
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11 years ago

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Thanks Rysc. All timings are met in all timing models. I don't use derive_pll_clocks because i'm the only designer and i like to keep the SDC clean. I did someresearch and TimeQuest didn't pick up the inverted clock signal simply because the -source was set to the PLL output and not to the NOT gate output. It was easier to simply use the -invert SDC option than to dig out the NOT gate output from the net list and use it as -source.

Thank you (and others) for your help. All I/Os have now been constrained in my design and i've learned a lot about TimeQuest the last few weeks. I now just have to debug my design to find out why it no longer works ;)

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Dear JohnG300C, I know this thread is very old. Can you please tell me the way you calculate 5.4ns for set_input_delay? I can not draw similar value when targeting an SDRAM. Thank you very much!