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Altera_Forum's avatar
Altera_Forum
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17 years ago

TimeQuest new user, trying to constrain clocks

I've created constraints for all the clocks that I know of in my design, but after I compile, and apply the SDC file, I end up with two unconstrained clocks:

fsk_demod:inst22|fsk_demod_GN:\fsk_demod_GN_0:inst_fsk_demod_GN_0|fsk_demod_GN_fsk_demod_bit_decoder0:fsk_demod_bit_decoder0_0|fsk_demod_GN_fsk_demod_bit_decoder0_process_between_zeros:fsk_demod_bit_decoder0_process_between_zeros_0|alt_dspbuilder_delay_GNGQ56ZS4N:Delay4|alt_dspbuilder_SDelay:Delay1i|result[0]

and

sopc_top:inst|cpu_0:the_cpu_0|M_alu_result[10]

From the names given, The first is a delay block within my DSP Builder design. I cannot figure out what I would set "period" to constrain this as a clock. I'm using it to latch data into a D-flipflop, so I guess I'm using it "as a clock" but not because it has a constant period.

The second is equally confusing to me, it's not a clock in the sense that I can think of.

Are these items I should declare "False" or something of that nature? I really don't care what the period is, more that the propagation is within reason (which is really quite flexible, I'm clocking bits through the latch at roughly 10 uS intervals.)

Thanks,

--Mickey

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Is this your own logic? In general, you don't want to use logic as a clock? For example, it would make sense to have this result[0] bit act as a clock enable to a register fed by the same clock. (result[0] is probably high for many clocks, so you also have to make it a pulse). This way everything is on a single clock domain and timing analysis is happy. This is very good practice to get into, and keping designs as synchronous as possible avoids headaches later on. Once you do this, you won't have to make any changes to your .sdc either.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    It is my own logic, Result[0] is a "valid" signal for an output, essentially a flag telling me the output of another section of my DSP Builder item is good to be sampled.

    Result[0] is high for one 100MHz clock cycle, which should trigger me to sample the output bit. I then need to stretch this output bit to 100 khz for my debugging test.

    The final implementation will not use the D-flip flop, but I need a 'quick and dirty' method to debug the DSP Builder portion, and I'm using DFF to build a signal I can sample on an oscilloscope. The final implementation will dump the serial data into bytes, put the bytes into a dual clock FIFO, and have SOPC builder read in the bytes, manipulate them, and send them out a UART.