Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

TimeQuest new user, trying to constrain clocks

I've created constraints for all the clocks that I know of in my design, but after I compile, and apply the SDC file, I end up with two unconstrained clocks: fsk_demod:inst22|fsk_demod_GN:\fsk_...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

It is my own logic, Result[0] is a "valid" signal for an output, essentially a flag telling me the output of another section of my DSP Builder item is good to be sampled.

Result[0] is high for one 100MHz clock cycle, which should trigger me to sample the output bit. I then need to stretch this output bit to 100 khz for my debugging test.

The final implementation will not use the D-flip flop, but I need a 'quick and dirty' method to debug the DSP Builder portion, and I'm using DFF to build a signal I can sample on an oscilloscope. The final implementation will dump the serial data into bytes, put the bytes into a dual clock FIFO, and have SOPC builder read in the bytes, manipulate them, and send them out a UART.