Forum Discussion
Altera_Forum
Honored Contributor
17 years agoIs this your own logic? In general, you don't want to use logic as a clock? For example, it would make sense to have this result[0] bit act as a clock enable to a register fed by the same clock. (result[0] is probably high for many clocks, so you also have to make it a pulse). This way everything is on a single clock domain and timing analysis is happy. This is very good practice to get into, and keping designs as synchronous as possible avoids headaches later on. Once you do this, you won't have to make any changes to your .sdc either.