Honored ContributorHello,
I'm not TQ expert, so I have some simple questions - how to constrain internal memory in fpga? Esp. dual-port RAM with different rd/wr clocks? Can single-port memory be constrained with "set_multicycle_path"? br
Honored Contributoran Altera Dual Clock FIFO will already have a set_false_path between the two domains
we'll need more information to see if a multicycle is the right solution for your single port RAMHonored ContributorI have a ROM memory with internally registered data output, so it takes 2 clocks to read. Because of this output register in path I'm not sure about using 'multicycle' in this case. Is there need to constrain the memory anyway?
Honored ContributorNo. Just constrain the clocks and the memory will be constrained from that.
