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Altera_Forum
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14 years ago

[TimeQuest] constraining block-RAM

Hello, I'm not TQ expert, so I have some simple questions - how to constrain internal memory in fpga? Esp. dual-port RAM with different rd/wr clocks? Can single-port memory be constrained with ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I have a ROM memory with internally registered data output, so it takes 2 clocks to read. Because of this output register in path I'm not sure about using 'multicycle' in this case. Is there need to constrain the memory anyway?