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Altera_Forum
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14 years ago

[TimeQuest] constraining block-RAM

Hello, I'm not TQ expert, so I have some simple questions - how to constrain internal memory in fpga? Esp. dual-port RAM with different rd/wr clocks? Can single-port memory be constrained with ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

an Altera Dual Clock FIFO will already have a set_false_path between the two domains

we'll need more information to see if a multicycle is the right solution for your single port RAM