TimeQuest and Fitter using SDC File

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1) Which commands should definitely be placed in the .sdc file? I'm trying to determine if there which commands to use, since the .sdc file is used for both timing-driven place and route and for timing analysis. It seems to be that all clock (including PLLs, etc) and I/O constraints should be placed in the .sdc file, and all other report_timing commands should be placed in separate .tcl scripts.

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Your last sentence is what Altera recommends. In addition, SDC commands like false-path exceptions belong in the .sdc file, and commands like create_timing_netlist should be in a .tcl file for a scripted setup.

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2) I'm familiar with Synopsys PrimeTime, so using TimeQuest is fairly straight-forward. However, there are differences in usage. Has anyone generated scripts or docs that described using the TimeQuest commands? I'm particularly interested in constraints applied to PLLs and to I/O.

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The examples that immediately come to mind are in training material, but this should also be covered in the Quartus handbook and examples at www.altera.com. The handbook has a chapter specifically on TimeQuest. The following chapter on switching to TimeQuest might also have some good examples. TimeQuest might be included in the training that you can access for free through the web site.

If you haven't found derive_pll_clocks yet, look up that one. It's covered in the Quartus on-line help.

Tony,

You can google "TimeQuest Design Example" to find a few basic SDC examples.

As Brad said, reading the Handbook chapter on TimeQuest is a good place to start.

If you want to quickly see all the commands supported by TimeQuest, go to your command console, and type "quartus_sh --qhelp". Then look for the "sdc", "sdc_ext" and "sta" Tcl packages. You will also find useful examples for every command.

Good luck.

I have some ideas on how to proceed forward with the timing analysis, but before I do, I wanted to see how other's have done it. I usually work on ASICs, and FPGAs are fairly new to me, having a reference would be a great help.

The most puzzling thing to me is generating a netlist based on either a slow or fast model. I'm used to writing a Verilog netlist, and SDF file, overlaying the timing information based on worst-case (slow) or best-case (fast) conditions, applying constraints, and generating timing reports.

It seems to me that whenever you run the TCL command "create_timing_netlist", you are actually creating a timing (SDF) file, or data set, based on the environment (fast or slow). It just seems a little cumbersome to create a new netlist every time you want to perform timing analysis.

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It just seems a little cumbersome to create a new netlist every time you want to perform timing analysis.

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You have to select a timing model when you create the timing netlist, but you can change the timing model with set_operating_conditions without deleting and recreating the timing netlist.

And here is an example:

http://www.altera.com/support/examples/timequest/exm-tq-multianalysis.html