Honored Contributor
Honored ContributorI have some ideas on how to proceed forward with the timing analysis, but before I do, I wanted to see how other's have done it. I usually work on ASICs, and FPGAs are fairly new to me, having a reference would be a great help.
The most puzzling thing to me is generating a netlist based on either a slow or fast model. I'm used to writing a Verilog netlist, and SDF file, overlaying the timing information based on worst-case (slow) or best-case (fast) conditions, applying constraints, and generating timing reports. It seems to me that whenever you run the TCL command "create_timing_netlist", you are actually creating a timing (SDF) file, or data set, based on the environment (fast or slow). It just seems a little cumbersome to create a new netlist every time you want to perform timing analysis.
