time constarint a clock generated by a counter

Hi Randeel,

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i have a module that runs on a clock generated by a counter,

so do i have to define that clock when i am time constraing the design

or just defining the main clock is enough?

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What is your application? Why do you need to generate a clock from a counter?

Normally generating clocks from your own logic (like your counter) is not good design practice.

You should use a PLL for generating clock signals with other frequencies than the external clock.

When time constraining your design you have to define constraints with respect to the clock(s) used in your design. In this way you can constrain the delay paths between outputs of registers clocked with one clock and inputs of registers (maybe clocked with an other clock).

I would suggest that you consider using a PLL in your design. You can use the ALTPLL module accessible via the MegaWizard to use in your design.

Hope this helps...

hi sanmao,

thank you for the reply.

my design is a uart, It derives (baudratex16) clk using a counter.

thank you,

randeel.

Generated clocks are usually considered bad practice.

Why not try using a clock enable

something like

baud : process(clock)

begin

...

if (clock'event and clock = '1') then

if (count = finalCount) then

count <= 0;

clockEnable <= '1';

else

count <= count + 1;

clockEnable <= '0';

end if;

end if;

end process baud;

other_stuff : process(clock)

begin

...

if (clock'event and clock = '1') then

if (clockEnable = '1') then

do stuff

end if;

end if;

end process other_stuff;

Everything is driven from the one clock but the logic in the second process is controlled by a clock enable signal from the baud rate process.

Hope this is of some help

Hi randeel,

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my design is a uart, It derives (baudratex16) clk using a counter.

randeel.

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Although many designers get tempted to generate clocks from their own logic to clock other registers, this should be avoided. You will create a lot of problems with races between signals and hazards setting/resetting registers.

Probably this is due to the fact that (still too many) textbooks on Digital Circuit Design are based on the emerging technolgies of the 1950's and 1960's. This results in unnecessary confusion. All of the examples with RS flip-flops, counters made out of T-flip-flops should be archived in the history books of Digital Circuit Technology.

Modern HDL synthesis tools detect this and discorage the use of such "derived clocks". In most designs you can realize a system in a nice synchronous way, only using one clock.

For a nice design of a UART you can have a look at: http://www.fpga4fun.com/serialinterface.html . This design uses the main clock of the system.

Hope this helps...

hello everyone,

thanks for the help.

i will change the design to single clock operated design as mentioned.

thank you,

randeel.

to constrain a ripple clock in TimeQuest use the Generated Clocks constraint on page 26:

http://www.altera.com/literature/hb/qts/qts_qii53018.pdf