time constarint a clock generated by a counter

Hi Randeel,

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i have a module that runs on a clock generated by a counter,

so do i have to define that clock when i am time constraing the design

or just defining the main clock is enough?

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What is your application? Why do you need to generate a clock from a counter?

Normally generating clocks from your own logic (like your counter) is not good design practice.

You should use a PLL for generating clock signals with other frequencies than the external clock.

When time constraining your design you have to define constraints with respect to the clock(s) used in your design. In this way you can constrain the delay paths between outputs of registers clocked with one clock and inputs of registers (maybe clocked with an other clock).

I would suggest that you consider using a PLL in your design. You can use the ALTPLL module accessible via the MegaWizard to use in your design.

Hope this helps...