time constarint a clock generated by a counter

Hi randeel,

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my design is a uart, It derives (baudratex16) clk using a counter.

randeel.

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Although many designers get tempted to generate clocks from their own logic to clock other registers, this should be avoided. You will create a lot of problems with races between signals and hazards setting/resetting registers.

Probably this is due to the fact that (still too many) textbooks on Digital Circuit Design are based on the emerging technolgies of the 1950's and 1960's. This results in unnecessary confusion. All of the examples with RS flip-flops, counters made out of T-flip-flops should be archived in the history books of Digital Circuit Technology.

Modern HDL synthesis tools detect this and discorage the use of such "derived clocks". In most designs you can realize a system in a nice synchronous way, only using one clock.

For a nice design of a UART you can have a look at: http://www.fpga4fun.com/serialinterface.html . This design uses the main clock of the system.

Hope this helps...