TEMPERATURE SENSOR IP in STRATIX10 SX , READ INCORRECT VALUE

Hi @WGith​

I managed to take a look into your design Demo_18_1_0_222_Temperature_IP.qar.

I dont see anything wrong with the Temperature and Voltage Sensor behaviour in your design as well.

I created another stp instance that only has the temp and voltage sensor.

Attached zip will have the stp file, and some screenshots that shows that it is working as expected.

JwChin, I tried my code with our custom board with a stratix 10 085 part on it. Using my desing, the temperature readings work, but still the voltage readings are completely incorrect. I will work to get your image working again with the new .stp file.

JwChin,

The larger issue is that even if I can get your image working, that just proves that the temperature and Voltage IP can work, which i assume it does. I need the temperature and voltage IP to work in MY design and as of now that is not the case. You have my simple design and it calls out the two IP blocks and makes sure to NOT access them at the same time. I also included a lot of delay timing so that should not be an issue. I dont know if the issue is due to be instantiating in VHDL versus Verilog, or if there is so other issue with how I am using the quartus software. Would it be possible for me to build my design for your test setup, all I would need is the a sample .qsf file from you with the pin locations for clock and reset. I can do everything automatically and you can see the output in signal tap.

FYI, I tried regenerating your design for our setup using the new stp file you sent me and I could not get the signaltap file to come up no matter what I tried. It kept saying that it was incompatible even though I made sure that the signal tap file was directly called out in the project file list and enabled and I definitely recompiled the design.

I am having an Arrow FAE come by tomorrow and I will set him up with your design and see if he can figure it out. I will also give him my design so he can work with other FAEs to see what is going on.

I fully suspect that there is an IP issue and that the two blocks are not interacting together correctly. In all honesty, since we are talking to a single ADC device, I dont understand why there isn't just one IP block and we address the voltage and temperature devices all in one.

JwChin, I know that I am doing something fundamentally wrong with your quartus archive, I just dont know what at the moment, and I don't have the time to figure it out. I already spent a lot of time trying to get your setup files working, and thats not what I need. If there is someone else who can assist me in getting the IP working using the cores I generated and my small state machine, that is what I ultimately need.

Hi @WGith​

Using your design, below are the screenshots of voltage reading.

It all looks correct to me.

May I know, using the same design, what reading/value did you get?

Hi JwChin,

I am the local Altera-dedicated FAE (with Arrow) working with Will on this problem.

I am attaching 3 screenshots of what Will is seeing in his system.

The Voltage_IP and Voltage_IP_2 (zoomed in picture of Voltage_IP) show Will sending a command but getting absolutely no response back. Voltage_IP shows the command being entered, Ready going low and then eventually going high with nothing happening in between. One thing that looks suspicious to Will and I is that Start of Packet and End of Packet are both a 1 and never go to 0.

Voltage_IP_3 shows the Ready signal never going high after a reset. Since Ready never goes active Will's state machine never issues a command which would be expected.

Could the problem that Will is seeing caused by the issue described here? -> https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/component/2018/the-clocks-and-resets-in-user-logic-must-be-gated-until-configur.html?wapkw=should+clocks+and+resets+in+user+logic+be+gated+until+the+configuration+process+is+completed

Steve Zack

JwChin,

One other thing - when you say you got Will's design to run can you describe on what board you did this on and what steps did you take to successfully run the code. Were you reading valid voltage and temperature readings?

Steve

Hi @SZack​

Stratix 10 Dev kit. https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s10-fpga.html

PN: 1SG280HU2F50E2VGS1

Yes, valid voltage and temperature.

btw, how is the simple design with tcl code coming by?

Hi @SZack​

No, I didn not use the Reset IP. I just run the design sent by Will as is. No modification done.

I only added some signals in signaltap, so that i can see the signals from the IP.