TEMPERATURE SENSOR IP in STRATIX10 SX , READ INCORRECT VALUE

hi, what is the value that you are reading? what is the expected temperature?

did you try the design in the how to video. https://www.youtube.com/watch?v=E5TaTxuOmOY&t=4s

Try downloading all the files in the youtube description. Run it and see if you still see any unexpected results. FYI, the design was tested working.

Hi,

I have the same issue as RYang6. The Voltage IP works fine for me, but the temperature IP for the Stratix 10 PCIE eval board gives extrememly sporadic or very weird readings. I have watched the youtube video and made sure my code is correct for decoding. i.e. one of the readings i get is 0xf240

Hi WGith,

Lets try this out:

1) can you use the exact design files in the youtube description. i want to Make sure we are on the same page and looking at the same design.

DOwnload the files and all the tcl scripts. Run it and see if you are getting the same results as shown in the youtube.

2) If you still see the sporadic problem, elaborate further what is the device P/N you are using. what quartus version are you using? how many boards tested & how many boards are seeing this problem? what is the expected temperature? how sporadic is the reading? does this happen to all channel or certain channels? can this be recovered by resetting the IP/ power cycling device?

I will more details in order to help you.

So I tried the Intel project and that did work. SO I dug deeper and opened the s10temp.ip that was included in that project. The ip opens the block symbol for that design has cmd_data of (6:0). That really surprised me as I know the temperature ip auto generated by quartus 18.0 and 18.1 has cmd_data at (8:0). Now this may not make a difference, but it IS different.

I am next going to try and build my design using the .ip from the Intel project and see if that works. If it does, then something is definitely wrong with the current IP block.

Hi @WGith​

Alternatively, use the Intel design that worked, upgrade the IP to 18.0 or 18.1. Confirm the bus width. Test it again. I think it is easier to debug from a working design.

Regards, jonway

Hi,

Here is my update. Using the IP from the working design with my code did work.....KIND OF. There is definitely something wrong with the IP block(S) and needs to be addressed soon. Using the working design IP, I was able to see the temperature for what I believe was the core logic temperature, but not the other Temperature I was requesting. Also I now see NONE of the voltage readings from the ADC, whereas before this was not an issue. So mixing the working temp IP with the working Voltage IP from Quartus do NOT work together. I had signal tap setup and in looking at the voltage output which is another block, I actually saw 2 of the voltage monitors sending data, but not int he voltage format, but in the temperature format. When I calculated them, these values appear to be valid, but slightly different temperautre readings than the temp IP block.

Now I know that the Voltage and Temperature IP all contact the ADC inside the FPGA. What I want to be able to do is have BOTH the Voltage and Temperature readings from the ADC. So, I'm not sure how to do that. I instantiated both blocks but they don't seem to be working together properly. Does the code to the ADC know to arbitrate between the two IP blocks correctly?

I will continue to work on this, but it would be good to have someone from Intel start looking at this in depth. I have using the S10 H-tile evaluation board.

Thank you,

Will

Hi,

Do I need to arbitrate between the Voltage IP and the Temperature IP blocks, meaning that only one of them can assert cmd_valid at a time, or does the IP blocks internally auto arbitrate?

I need to be able to find a combination of IP blocks that work so I can access both the voltage and temperature readings.

Any assistance you can provide in escalating this would be appreciated as there is definitely something not right with the current IP blocks.

Hi @WGith,

Yes, you need to arbitrate the cmd_valid between both Voltage IP and Temperature IP. No, it doesnt auto arbitrate.

Regarding your earlier concern on additional 2 bits in the cmd_data. [6:0] to [8:0}. In 18.1, 2 channels are added for temperature sensing at HBM (for devices that supports it).

I hope this clears your doubt.

Hi,

I appreciate the help you have been giving me, but there is still something not right with the design. I have updated the design to poll the voltage monitor ip and then the temperature ip and keep looping on that. This still doesn't work for me. I will try to find some time to generate a signaltap enabled image to give you additional information.