Forum Discussion
Hi,
Here is my update. Using the IP from the working design with my code did work.....KIND OF. There is definitely something wrong with the IP block(S) and needs to be addressed soon. Using the working design IP, I was able to see the temperature for what I believe was the core logic temperature, but not the other Temperature I was requesting. Also I now see NONE of the voltage readings from the ADC, whereas before this was not an issue. So mixing the working temp IP with the working Voltage IP from Quartus do NOT work together. I had signal tap setup and in looking at the voltage output which is another block, I actually saw 2 of the voltage monitors sending data, but not int he voltage format, but in the temperature format. When I calculated them, these values appear to be valid, but slightly different temperautre readings than the temp IP block.
Now I know that the Voltage and Temperature IP all contact the ADC inside the FPGA. What I want to be able to do is have BOTH the Voltage and Temperature readings from the ADC. So, I'm not sure how to do that. I instantiated both blocks but they don't seem to be working together properly. Does the code to the ADC know to arbitrate between the two IP blocks correctly?
I will continue to work on this, but it would be good to have someone from Intel start looking at this in depth. I have using the S10 H-tile evaluation board.
Thank you,
Will