Takes too long to get address

write enable should be applied at the same clock cycle as the write address. In your code, write enable is supplied from the port directly, but address registered and thus one cycle delayed. If address is a registered signal, write enable should be as well. But the address is already registered in the RAM block, so it can be assigned outside the clocked process code.

I don't really follow 100%. You're saying that the lines

if(valid_RE or readEn_RE) then
				address <= rwaddressstart;
			elsif(valid = '1' or readEn = '1') then
				address <= address + '1';

You need to register the valid input to align it with the address signal you are creating and connect the registered version of it to the write-enable port of the ram.

Register both or none of the RAM block input signals.

When you say register valid, does that mean, just assign it to a signal?

I mean register the incoming valid signal and change the port map of the store like this

   signal valid_r : std_logic;
begin
  
  process(clk, reset)
  begin
    if reset = '1' then
      valid_r <= '0';
    elsif rising_edge(clk) then
      valid_r <= valid;
    end if;
  end process;
  
  
  store: ram4bits 
  port map (
    address => address,
    clock   => clk,
    data    => input,
    wren    => valid_r,
    q       => hold
  );

What does it mean to change the portmap to be what you specified? I'm not famililar with the => notation. I changed it to exactly how you specified but I'm still missing the first value that I try to write. To me it looks like the first value is just never written to memory. To test it out I made a simple wave form with a valid signal that's high for a cycle (starting when clock is low, ending when clock is high) and I also have an input in that same cycle. At the falling edge, I see my output for the rising edge, and thats when the address appears but that first value isn't written.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; 
entity framestore is
	port
	(
		clk,reset : in std_logic;
		input: in std_logic_vector(3 downto 0);
		valid: in std_logic;
		readEN: in std_logic;
		rwaddressstart: in std_logic_vector(14 downto 0);
		output : out std_logic_vector(3 downto 0);
		addressout: out std_logic_vector(14 downto 0);
		holdout: out std_logic_vector(3 downto 0);
		validreout: out std_logic;
		readreout: out std_logic
	);
end framestore;
architecture structure of framestore is
	signal hold: std_logic_vector(3 downto 0);
	signal address: std_logic_vector(14 downto 0);
	signal tempvalid: std_logic;
	signal tempread: std_logic;
	signal readEn_RE: boolean;
	signal valid_RE: boolean;
	signal reg: std_logic;
	
	component ram4bits is
	PORT
	(
		address		: IN STD_LOGIC_VECTOR (14 DOWNTO 0);
		clock		: IN STD_LOGIC  := '1';
		data		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		wren		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
	);
	end component;
begin	
	process(clk,reset,valid,readEn)
	begin
		if(reset = '1') then
			address <= "000000000000000";
			reg <= '0';
		elsif(clk'event and clk = '1') then
			reg <= valid;
			if(valid_RE or readEn_RE) then
				address <= rwaddressstart;
			elsif(valid = '1' or readEn = '1') then
				address <= address + '1';
			end if;
		elsif(clk'event and clk = '0') then
			tempread <= readEn;
			tempvalid <= valid;
		end if;
	end process;
	
	store: ram4bits port map(address => address,clock => clk,data => input,wren => reg,q=>hold);
	
	readEn_RE <= tempread = '0' and readEn = '1';
	valid_RE <= tempvalid = '0' and valid = '1';
	output <= hold when readEn = '1' else "0000";
	
	validreout <= '1' when valid_RE else '0';
	readreout <= '1' when readEn_RE else '0';
	addressout <= address;
	holdout <= hold;
	
end structure;

Can you post an image of the output waveform? it sounds like your input and valid signal may be missaligned.

Sure thing. Thanks a bunch

My input and valid appear to arrive at exactly the same time, which is how I set it in my wavefunction.