Takes too long to get address

What does it mean to change the portmap to be what you specified? I'm not famililar with the => notation. I changed it to exactly how you specified but I'm still missing the first value that I try to write. To me it looks like the first value is just never written to memory. To test it out I made a simple wave form with a valid signal that's high for a cycle (starting when clock is low, ending when clock is high) and I also have an input in that same cycle. At the falling edge, I see my output for the rising edge, and thats when the address appears but that first value isn't written.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; 
entity framestore is
	port
	(
		clk,reset : in std_logic;
		input: in std_logic_vector(3 downto 0);
		valid: in std_logic;
		readEN: in std_logic;
		rwaddressstart: in std_logic_vector(14 downto 0);
		output : out std_logic_vector(3 downto 0);
		addressout: out std_logic_vector(14 downto 0);
		holdout: out std_logic_vector(3 downto 0);
		validreout: out std_logic;
		readreout: out std_logic
	);
end framestore;
architecture structure of framestore is
	signal hold: std_logic_vector(3 downto 0);
	signal address: std_logic_vector(14 downto 0);
	signal tempvalid: std_logic;
	signal tempread: std_logic;
	signal readEn_RE: boolean;
	signal valid_RE: boolean;
	signal reg: std_logic;
	
	component ram4bits is
	PORT
	(
		address		: IN STD_LOGIC_VECTOR (14 DOWNTO 0);
		clock		: IN STD_LOGIC  := '1';
		data		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		wren		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
	);
	end component;
begin	
	process(clk,reset,valid,readEn)
	begin
		if(reset = '1') then
			address <= "000000000000000";
			reg <= '0';
		elsif(clk'event and clk = '1') then
			reg <= valid;
			if(valid_RE or readEn_RE) then
				address <= rwaddressstart;
			elsif(valid = '1' or readEn = '1') then
				address <= address + '1';
			end if;
		elsif(clk'event and clk = '0') then
			tempread <= readEn;
			tempvalid <= valid;
		end if;
	end process;
	
	store: ram4bits port map(address => address,clock => clk,data => input,wren => reg,q=>hold);
	
	readEn_RE <= tempread = '0' and readEn = '1';
	valid_RE <= tempvalid = '0' and valid = '1';
	output <= hold when readEn = '1' else "0000";
	
	validreout <= '1' when valid_RE else '0';
	readreout <= '1' when readEn_RE else '0';
	addressout <= address;
	holdout <= hold;
	
end structure;