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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Takes too long to get address

I'm writing a simple program that reads and writes to RAM. If I want to write, I provide the starting address and a valid signal and I write to memory starting at that address until valid is deasser...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I mean register the incoming valid signal and change the port map of the store like this 


   signal valid_r : std_logic;
begin
  
  process(clk, reset)
  begin
    if reset = '1' then
      valid_r <= '0';
    elsif rising_edge(clk) then
      valid_r <= valid;
    end if;
  end process;
  
  
  store: ram4bits 
  port map (
    address => address,
    clock   => clk,
    data    => input,
    wren    => valid_r,
    q       => hold
  );