Honored ContributorI have files written in SystemVerilog but they are saved with the extension .v
Does the Quartus support SystemVerilog design files? What do I need to do for the SystemVerilog files but saved in .v extension? Thanks.
Honored ContributorAlternatively you can place this commented out line at the top of your SystemVerilog file (if you don't want to declare your whole project to be SystemVerilog):
// synthesis VERILOG_INPUT_VERSION SYSTEMVERILOG_2005Honored ContributorHello,
I would have thought all you would need to do is change the file extension to .sv jtHonored ContributorQuartus projects treat .v & .sv files the same way: according to Settings -> Analysis & Synthesis Settings -> Verilog HDL Input -> Verilog version. By default it's Verilog-2001. Set to SystemVerilog-2005 to enable use of sv keywords and features.
Honored ContributorIf you set the global option to "SystemVerilog" then all files (*.v or .sv) will be synthesized with SV extensions. If you use .sv in your extension, then Quartus will us SV for those files. In the .qsf there is a different keyword for SV.
set_global_assignment -name SYSTEMVERILOG_FILE ../src/I2C_Master_PSOC/I2C_Master_PSOC_IF.sv set_global_assignment -name VERILOG_FILE ../src/VCCIO_Controller/LTC2620.v Ed
