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Altera_Forum
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17 years ago

SystemVerilog supported by Quartus?

I have files written in SystemVerilog but they are saved with the extension .v Does the Quartus support SystemVerilog design files? What do I need to do for the SystemVerilog files but saved in ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

If you set the global option to "SystemVerilog" then all files (*.v or .sv) will be synthesized with SV extensions. If you use .sv in your extension, then Quartus will us SV for those files. In the .qsf there is a different keyword for SV.

set_global_assignment -name SYSTEMVERILOG_FILE ../src/I2C_Master_PSOC/I2C_Master_PSOC_IF.sv

set_global_assignment -name VERILOG_FILE ../src/VCCIO_Controller/LTC2620.v

Ed