synthesis have a wrong result when some logic in generate block

Look at the synthesis result that you think is wrong, the logic for register "ror_size_ex[2]" should be working as this:

1) when dsp_...[17:16] =2 'b0,

cx_b_dsp_i[2] => ror_size_ex[2]

2) when dsp_...[17:16] =2 'b1,

cx_b_dsp_i[10] => ror_size_ex[2]

3) when dsp_...[17:16] =2 'b10,

cx_b_dsp_i[18] => ror_size_ex[2]

4) when dsp_...[17:16] =2 'b11,

cx_b_dsp_i[26] => ror_size_ex[2]

Why it is connected to GND for case 1 & 2, I think that signal "dsp_...[17]" is always high in your coding and make them never happened. Please trace that signal/variable how it is connected. Not sure this would address your question.