New Contributor
ContributorHi wsive, today I got again similar issue, I am suspecting some issue by file size and or long comment.
They appear and disappear, few hour ago I got deterministic stable behavior, if elsif generate wrong network, case instead generate ok also cleaning project.
After some change to file removing large commented block issue disappeared and never appeared till now using if elsif was stable errantic.....
From error issue to now the version where wrong now compile fine.
I am using VHDl but I observed some similar issues also on verilog and your file has near 1K lines like mine.
Try add a large code commented block (100 lines or more) before and after and see what happen. No more idea for now, I seen other observe intermittent issue.
Regards
New Contributorthanks for relay. do you mean, I need try to add a large code commented block (100 lines or more) before the generate block and after the generate block?
the commented block may like below:
/*
-------
-------
-------
...
---------
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*/
Contributorhi Wsiwe, yes that what I observed, took some code, not garbage, copy paste then comment out. generally I leave between code I rewrote and at end when change apply'd to new code.
I am trying on Linux took 1 minute to build, when I am sure or close to of what trigger this I can try on other platform.
One time I try'd leave compiling on Win7, same behavior, but appear and disappear in a while.
I am also parallel installing last Ubuntu version to avoid comment from Intel clerks and close the loop to culprit of.
Good answer to this was to change vendor, I am too close to deadline.
My Hardware is intended controlling a mechanical with huge moving part and cannot risk the life of none. This is not a game.
Regards
Robert
