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wsiwe's avatar
wsiwe
Icon for New Contributor rankNew Contributor
7 years ago

synthesis have a wrong result when some logic in generate block

Quartus version is 16.1 lite and 18.1 lite. As RTL, ror_size_ex is from dsp_…[17:16], when dsp_...[17:16] is 0, , it should be cx_b_dsp_i But see the synthesis result, when dsp_...[17:16] is 0, ...
Abe's avatar
Abe
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Can you post the code or the QAR file for the project. We need the code/project to check it.