Synthesis error while using interface parameters

Hi

I have come across an issue with Quartus synthesis. As shown in the code below, I have defined a simple `data_stream_i` interface and a simple `demux` module (Demux 1 channels to 2 channels using dest signal for routing). I was trying to use parameters from the input interface (`i_in`) to instance another, internal interface (`i_in_reg`). Unfortunately, the module fails to synthesize - I get `Error(13433): Verilog HDL Defparam Statement error at demux.sv(8): value for parameter "TDATA_T_WIDTH" must be constant expression`.

I have come to the conclusion that the `i_in_reg` interface can not be created with the `data_t` type, as long as the `TDATA_WIDTH` parameter is assigned to any of the `data_stream_i` interface parameters.

This error’s cause is described as: “In a Defparam Statement at the specified location in a Verilog Design File (.v), you specified a value for the specified parameter that is not a constant expression. You must specify only constant expressions for parameter values.” (here). However, all values used by me are, in fact, constant. Moreover, this code can be synthesized with Vivado.

Could you help me with this issue?

Thank you in advance!

Steps to replicate:

1. Use `Quartus Prime Pro Edition 20.4.0` with any devices installed
2. Create a new project, add following code to `demux.sv` file.
3. Set `demux.sv` as Top-level Entity
4. Run `Analysis & Synthesis`
   

Used code:

/*
 * Demux 1 channels to 2 channels using dest signal for routing
 */
 
 interface data_stream_i #(
    parameter DATA_WIDTH = 512,
    type TDATA_T = logic [DATA_WIDTH-1:0],
    parameter TDATA_T_WIDTH = $bits(TDATA_T)
) ();
    logic   tvalid;
    logic   tready;
    TDATA_T tdata;

    modport master (
        output tdata,
        input  tready,
        output tvalid
    );

    modport slave (
        input  tdata,
        output tready,
        input  tvalid
    );

endinterface : data_stream_i

 
module demux #()(
    input logic          clk,
    input logic          reset,
    data_stream_i.slave  i_in,
    data_stream_i.master i_out[1:0],
    input logic			 dest
);

    localparam TDATA_WIDTH = i_in.TDATA_T_WIDTH;

	 //Using data_t as TDATA_T type triggers: Error(13433): Verilog HDL Defparam Statement error at axis_demux.sv(8): value for parameter "TDATA_T_WIDTH" must be constant expression 
	 //This is true for: TDATA_WIDTH = i_in.TDATA_T_WIDTH; TDATA_WIDTH = $bits(i_in.TDATA_T); and TDATA_WIDTH = i_in.DATA_WIDTH
	 //Defining TDATA_WIDTH = 512; results in successful synthesis
    typedef struct packed {
        logic [TDATA_WIDTH-1:0] base;
        logic                   dest;
    } data_t;

    data_stream_i #(.TDATA_T(data_t)) i_in_reg();
    logic [1:0] out_reg_tready;

    assign i_in_reg.tvalid  	 = i_in.tvalid;
    assign i_in.tready      	 = out_reg_tready[i_in_reg.tdata.dest];
    assign i_in_reg.tdata.base = i_in.tdata;
    assign i_in_reg.tdata.dest = dest;

    generate
        for (genvar i=0; i < 2; i++) begin : OUTPUT_REG
            assign out_reg_tready[i] = i_out[i].tready;
            assign i_out[i].tvalid 	= i_in_reg.tdata.dest == i ? i_in_reg.tvalid : 1'b0;
            assign i_out[i].tdata  	= i_in_reg.tdata;;
        end
    endgenerate

endmodule : demux