New Contributor
New ContributorNo - I did not. "type" is a keyword for TDATA_T parameter.
This module can be synthesized if I pass `512` value to TDATA_WIDTH parameter:
localparam TDATA_WIDTH = 512;
The rest of this code is correct and does not cause any errors..
Super ContributorThis could be potential bug. I have filed a case to engineering team to check on this.
Please do expect that any work that involve engineering may takes some time, depending on the issue complexity.
Best Regards,
Shyan Yew (Richard)
New ContributorSuper ContributorHere's the feedback from the engineering team:
-start-
SystemVerilog 1800-2012 LRM section 23.10.4.1 explains the order of elaboration and it says
"The following algorithm defines an order that produces the correct hierarchy:
a) A list of starting points is initialized with the list of top-level modules.
b) The hierarchy below each starting point is expanded as much as possible
without elaborating generate constructs. All parameters encountered during this
expansion are given their final values by applying initial values, parameter
overrides, and defparam statements."
In this case, the value of parameter in one interface depends on parameter declared in sibling hierarchy (interface). So it is not possible to evaluate such parameter expressions in hier-tree creation process.
Also if you will try the design in VCS and QuestaSim you will see similar errors.
We have a new more advanced hierachy tree flow enables in later builds e.g. 21.1 where we have better and more stricter language standard checks. So that is the reason we slipped this in previous release but erroring it out now.
-end-
Based on the feedback, it seems that this will not be supported in the Quartus, attached the workaround wrote by the engineer though it may not be robust enough. Attached the .zip file with the .sv file in it.
Let me know if you have further question.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
New ContributorThank you for your response. You are right about the code I have provided. I was unable to simulate it with QuestaSim as well.
** Error: (vsim-8894) q_bug.sv(37): In instance "demux", parameter reference "i_in.TDATA_T_WIDTH" through interface port "i_in" is not valid when the actual interface in the instance is an arrayed instance element or below a generate construct.
But, all I have to do in order to be in line with SystemVerilog 1800-2012 LRM is to add following top module.
module top( input logic clk, input logic reset, input logic dest, input logic in_tvalid, output logic in_tready, input logic[511:0] in_tdata, output logic out0_tvalid, input logic out0_tready, output logic[511:0] out0_tdata, output logic out1_tvalid, input logic out1_tready, output logic[511:0] out1_tdata ); data_stream_i in(); data_stream_i out[1:0](); assign in.tvalid = in_tvalid; assign in.tdata = in_tdata; assign in_tready = in.tready; assign out0_tvalid = out[0].tvalid; assign out0_tdata = out[0].tdata; assign out[0].tready = out0_tready; assign out1_tvalid = out[1].tvalid; assign out1_tdata = out[1].tdata; assign out[1].tready = out1_tready; demux dut( .clk ( clk ), .reset ( reset ), .dest ( dest ), .i_in ( in ), .i_out ( out ) ); endmodule
Now, this code can be simulated with QuestaSim, but I still get an error with Quartus:
Error(13433): Verilog HDL Defparam Statement error at demux.sv(8): value for parameter "TDATA_T_WIDTH" must be constant expression
Could you please help me with this issue? Thank you in advance!
Best regards,
Piotr Wzorek
