Synthesis error while using interface parameters

Here's the feedback from the engineering team:

-start-

SystemVerilog 1800-2012 LRM section 23.10.4.1 explains the order of elaboration and it says

"The following algorithm defines an order that produces the correct hierarchy:
a) A list of starting points is initialized with the list of top-level modules.
b) The hierarchy below each starting point is expanded as much as possible
without elaborating generate constructs. All parameters encountered during this
expansion are given their final values by applying initial values, parameter
overrides, and defparam statements."

In this case, the value of parameter in one interface depends on parameter declared in sibling hierarchy (interface). So it is not possible to evaluate such parameter expressions in hier-tree creation process.

Also if you will try the design in VCS and QuestaSim you will see similar errors.

We have a new more advanced hierachy tree flow enables in later builds e.g. 21.1 where we have better and more stricter language standard checks. So that is the reason we slipped this in previous release but erroring it out now.

-end-

Based on the feedback, it seems that this will not be supported in the Quartus, attached the workaround wrote by the engineer though it may not be robust enough. Attached the .zip file with the .sv file in it.

Let me know if you have further question.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.