Synthesis error in VHDL process

Hi,

I am trying to implement clock synchronizer and clock divider in the following piece of VHDL code. The clocks(clk_rx and clk_tx) should synchronize at the rising and falling edges of 'RX' signal on the bus. I can simulate the following in Modelsim but it is not synthesizable in ISE since i am using " RX'EVENT ". Could any one suggest an alternative for this? (vhdl or verilog)

-------------------------------------------- CLOCK DIVIDER----------------------------------------------------------------------------------------

PROCESS (CLK_I, RX)

BEGIN

IF (RX'EVENT) THEN

clk_cnt <= to_unsigned(0,clk_cnt'LENGTH);

ELSIF (CLK_I'EVENT AND CLK_I = '1') THEN

IF clk_cnt >2499 THEN

clk_cnt <= to_unsigned(0,clk_cnt'LENGTH);

ELSE

clk_cnt <= clk_cnt + 1;

END IF;

END IF;

END PROCESS;

clk_rx <= '1' WHEN clk_cnt = 1250 ELSE '0'; -----clk_rx=1 only at the half of the counter period----------clk enable

clk_tx <= '1' WHEN clk_cnt = 2499 ELSE '0';