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Altera_Forum
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12 years ago

Synthesis error in VHDL process

Hi, I am trying to implement clock synchronizer and clock divider in the following piece of VHDL code. The clocks(clk_rx and clk_tx) should synchronize at the rising and falling edges of 'RX' s...
Altera_Forum's avatar
Altera_Forum
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12 years ago

you cant detect both edges of the RX signal, you are only allowed to detect a single rising or falling edge, and us it as the clock - not in addition to another clock.

What is RX? is it really a clock or some other signal? usually you would create an edge detector by comparing a registered version of a signal to the signal itself.

It simulates fine because lots of VHDL works fine in simulation but is no use for synthesis.