Synthesis error in VHDL process

Thanks for the reply. RX is the receiver pin. I am implementing a protocol similar to CAN. The module is connected to wishbone bus. So CLK_I is wishbone clock.

The specification says I should synchronize to both edges of RX. I have changed the code little bit to compare the registered version of RX. Is this what you mean?

PROCESS (CLK_I)

BEGIN

IF (CLK_I'EVENT AND CLK_I = '1') THEN

tmp_RX <= RX;

IF (RX /= tmp_RX) THEN

clk_cnt <= to_unsigned(0,clk_cnt'LENGTH);

ELSIF clk_cnt >2499 THEN

clk_cnt <= to_unsigned(0,clk_cnt'LENGTH);

ELSE

clk_cnt <= clk_cnt + 1;

END IF;

END IF;

END PROCESS;