KarelSterckx
Occasional Contributor
2 years agoSyntax error in initial block
I am using Quartus Prime Lite Edition v22.1.1
In my Verilog HDL code, I include the following initial block:
initial begin
div = 4’b0;
lpc = 4’b0;
pa = 4’b0;
plc_lsb = 8’b0;
plc_usb = 8’b0;
dsb = 9’b0;
end
A syntax error in every line of the initial block is generated when I compile the code. I do not see anything wrong with the code though.
Thanks a lot. That is indeed the problem. I have no idea how that back tick crept in as I do not have it on my keyboard. Perhaps I copied it from somewhere though I cannot remember.