Occasional ContributorThanks a lot. That is indeed the problem. I have no idea how that back tick crept in as I do not have it on my keyboard. Perhaps I copied it from somewhere though I cannot remember.
Frequent ContributorYou need to provide more info.
What exactly is the error message(s) that are being generated?
What is the code context of the initial block (ie, the verilog code before the block).
Guessing it could be the initial block is not valid in that context, or the items you assign in the block are not reg variables.
Occasional ContributorThe error messages for each line within the initial block are:
Error (10170): Verilog HDL syntax error at dsb.v(10) near text: . Check for and fix any syntax errors that appear immediately before or at the specified keyword.
Error (10170): Verilog HDL syntax error at dsb.v(10) near text: " "; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword.
Code before the initial block is:
module dsb (clk_c, plc_lsb, plc_usb, dsb);
input clk_c;
output plc_lsb, plc_usb, dsb;
reg [3:0] div, lpc, pa; // div = counter used to obtain clk_m from clk_c
wire [3:0]sub, add;
reg [7:0] plc_lsb, plc_usb;
reg [8:0] dsb;
initial begin
div = 4’b0;
lpc = 4’b0;
pa = 4’b0;
plc_lsb = 8’b0;
plc_usb = 8’b0;
dsb = 9’b0;
end
