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KarelSterckx's avatar
KarelSterckx
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2 years ago
Solved

Syntax error in initial block

I am using Quartus Prime Lite Edition v22.1.1 In my Verilog HDL code, I include the following initial block: initial begin div = 4’b0; lpc = 4’b0; pa = 4’b0; plc_lsb = 8’b0; plc_usb = 8’b0; ...
  • KarelSterckx's avatar
    KarelSterckx
    2 years ago

    Thanks a lot. That is indeed the problem. I have no idea how that back tick crept in as I do not have it on my keyboard. Perhaps I copied it from somewhere though I cannot remember.