Synopsys SDC asyncronous clock

I have a design that uses memory mapped registers in an FPGA connected to a bus using an NXP processor. The bus consists of a data bus, address bus, chip enable, and read and write lines. I'm not sure how to constrain this ansycronous design. The read and write signals are getting flagged as unconstrained clocks. I believe that I need to constrain those as clocks and then setup input and output delays based on the read and write signals? Would someone have an idea or an example as to the proper way to constrain a design like this?

I appreciate any help that someone might have!

Have a good day!

Brandon