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BTayl147's avatar
BTayl147
Icon for New Contributor rankNew Contributor
4 years ago

Synopsys SDC asyncronous clock

I have a design that uses memory mapped registers in an FPGA connected to a bus using an NXP processor. The bus consists of a data bus, address bus, chip enable, and read and write lines. I'm not ...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


We did not receive any response to the previous reply provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards,

Nurina


P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution.