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Altera_Forum's avatar
Altera_Forum
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10 years ago

Support Vector Machine VHDL

I would like to know if there someone has a VHDL code for Support Vector Machine.

I would also like to know if someone could explain to me this line of code

res: out sfixed(7 downto -10)

I know what is downto, but I have never seen it to a negative number before.

Does that mean this is sfixed is 17 bits? If so why not 16 downto 0

Thanks

I also attached an SVM code that I understand but having trouble some parts.

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Its actually 18 bits signed fixed point number, with 8 bits integer and 10 bits fractional.

    The sfixed/ufixed types were added with VHDL 2008 (there is a 1993 compatability library). It allows you to represent fixed point numbers a bit more easily (and slightly less confusingly). Positive indexes are the integer part, and -ve are the fractional parts.

    eg. res : sfixed(1 downto -2) := "0101";

    = 1.25

    "0011" = 0.75
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    I would like to know if there someone has a VHDL code for Support Vector Machine.

    I would also like to know if someone could explain to me this line of code

    res: out sfixed(7 downto -10)

    I know what is downto, but I have never seen it to a negative number before.

    Does that mean this is sfixed is 17 bits? If so why not 16 downto 0

    Thanks

    I also attached an SVM code that I understand but having trouble some parts.

    --- Quote End ---

    Please Sir, I need your help in making me understand this line

    use ieee.fixed_pkg.all

    when I ran the program, I found this problem

    ERROR:HDLParsers:3014 - "C:/Users/George1/Desktop/fixed_top.vhd" Line 4. Library unit fixed_pkg is not available in library ieee.

    I need the library please.

    Thank you so much
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    I would like to know if there someone has a VHDL code for Support Vector Machine

    --- Quote End ---

    Doing a quick search o the Web, we can find some academic researches and even working implementations on VHDL, but I would be cautious in regard to find some really trustworthy code. The LibSVM is a well known and reliable library, but wrote in C, with which you could consider running under a softcore environment, although loosing some performance in terms of speed if compared to a hardware-based implementation.
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    Please Sir, I need your help in making me understand this line

    use ieee.fixed_pkg.all

    when I ran the program, I found this problem

    ERROR:HDLParsers:3014 - "C:/Users/George1/Desktop/fixed_top.vhd" Line 4. Library unit fixed_pkg is not available in library ieee.

    I need the library please.

    Thank you so much

    --- Quote End ---

    How are you trying to compile the code?

    the fixed_pkg is part of the VHDL 2008 standard and is included with modelsim. For Quartus prime 15.1 and later, the package is included. For earlier versions, you need to find a version of the library from somewhere.
  • Altera_Forum's avatar
    Altera_Forum
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    >For Quartus prime 15.1 and later, the package is included.

    only PRO edition (aka ARRIA 10)
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    How are you trying to compile the code?

    the fixed_pkg is part of the VHDL 2008 standard and is included with modelsim. For Quartus prime 15.1 and later, the package is included. For earlier versions, you need to find a version of the library from somewhere.

    --- Quote End ---

    I am compiling the code with Xilinx ISE.

    You are right when I compile it with Modelsim, it runs with no error.

    How can I compile with Xilinx
  • Altera_Forum's avatar
    Altera_Forum
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    You'll need to get hold of the Xilinx version of the fixed_pkg that is '93 compatible.

    And you'll get more help on the Xilinx forum (this is a altera forum, Xilinx competitor.)