Support Vector Machine VHDL

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I would like to know if there someone has a VHDL code for Support Vector Machine.

I would also like to know if someone could explain to me this line of code

res: out sfixed(7 downto -10)

I know what is downto, but I have never seen it to a negative number before.

Does that mean this is sfixed is 17 bits? If so why not 16 downto 0

Thanks

I also attached an SVM code that I understand but having trouble some parts.

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Please Sir, I need your help in making me understand this line

use ieee.fixed_pkg.all

when I ran the program, I found this problem

ERROR:HDLParsers:3014 - "C:/Users/George1/Desktop/fixed_top.vhd" Line 4. Library unit fixed_pkg is not available in library ieee.

I need the library please.

Thank you so much