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Honored Contributor
Honored ContributorSupport Vector Machine VHDL
I would like to know if there someone has a VHDL code for Support Vector Machine. I would also like to know if someone could explain to me this line of code res: out sfixed(7 downto -10)...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- How are you trying to compile the code? the fixed_pkg is part of the VHDL 2008 standard and is included with modelsim. For Quartus prime 15.1 and later, the package is included. For earlier versions, you need to find a version of the library from somewhere. --- Quote End --- I am compiling the code with Xilinx ISE. You are right when I compile it with Modelsim, it runs with no error. How can I compile with Xilinx
