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Balkesh's avatar
Balkesh
Icon for New Contributor rankNew Contributor
1 year ago

Support Logic Generation Error

Hi, I have got a error while executing a programm in Quatus prime pro software v23.1 the device i use to run the project was agib023r18a1e1v. If i execute the same module by making top then didn't g...
Hdl
Harshx's avatar
Harshx
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi,

Thanks for contacting Intel. I'm assigned to support request.

I'll investigate on this case and get back to you soon once I have any finding.

Meanwhile can I check with you on

  1. Please share the IP names you are using in your design.
  2. Is it possible for you to share archived design? If yes, kindly attach.

Thanks for your patience.

Best regards,

Harsh M


Beginner_in_FPGA's avatar
Beginner_in_FPGA
Icon for Contributor rankContributor
1 year ago

Hi @Harshx ,


I too am facing the same issue when using an F-Tile for the device AGI027R31B1E1V and Quartus 24.1 Prime Pro. Design in question is the Intel OFS F-Tile Design which I am porting to my own custom board.

I have changed the Ethernet Subsystem to a single port 400GCAUI-4 using the 4 FHT Channels in one F-Tile and am using my own constraints. When compiling the same error pops up.

Error(22241): Cannot place the block hssi_wrapper|hssi_ss|hssi_ss|U_eth_f_inst_p16|eth_f_top_p16|hip_inst|per_xcvr[0].x_bb_f_bk at location fht_ch0 because it uses port next_bonding_link that is not present at this location.

Any updates on this case? It would be greatly helpful.

Thank you,
Best Regards.