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Harshx
Occasional ContributorJoined 2 years ago
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Re: Hardware Implementation of Intel JESDIP Core with Agilex 7 and AFe7950EVM
Hi, It seems you have no proper clock in your design. You can check using BTS(Board test system) Go to your Development Kit user guide, check under Board Test System section (example: 4.3. Control On-board Clock through Clock Controller GUI). Kindly download installer package for your device from intel (Agilex™ 7 FPGA I-Series Development Kit (2x R-Tile and 1x F-Tile)) from there check DV kit user guide-> Board Test System section. You need to align the proper clock to the pin you have selected in design (Use schematic from the package to check for clock pins) Regards, Harsh M1.3KViews0likes0CommentsRe: Hardware Implementation of Intel JESDIP Core with Agilex 7 and AFe7950EVM
Hi, Thanks for contacting Intel. I'm assigned to support request. I'll investigate on this case related and get back to you soon once I have any finding. Meanwhile can I check with you on: Quartus version OPN number Clock is stable? (have you checked it with CRO), since you are having issue with both example design as well as custom one. Check for any warnings while IP generation and timing issues. Have you checked with preset example design (since you mentioned that you have generated example design with your configurations). Thanks for your patience. Best regards, Harsh M1.4KViews0likes1CommentRe: XCVR Reset Controller
Hi, Do you have any error messages in the "messages" window? What do you mean by "The JTAG Master is recognized in System Console but Toolkit does not recognize any debug endoiint" ? The design is loading properly? and is in reset or not? Regards, Harsh M2.9KViews0likes2CommentsRe: oc-3/oc-12 mapper framer
Hi, Thanks for contacting Intel. I'm assigned to support request. Kindly check for various IPs for your related speed in Intel FPGA transceivers. e.g. JESD204B/C or PMA and FEC Direct PHY IP. You also need to check for what type of transceiver (H-tile, F-tile etc ) you are going to use as per your required speed range. Best regards, Harsh M326Views0likes0CommentsRe: Agilex E-Tile-Error(20672): For HSSI E-tile, there is no path between HSSI REFCLK and core
Hi, The file you shared is just qpf file of the project which have no details about the project. You can check clock details here: 1.6.1. Design Example Components (intel.com) Regards, Harsh M573Views0likes0CommentsRe: Agilex 7 E-tile Eye diagram viewer failure
Hi, Thanks for contacting Intel. I'm assigned to support request. I'll investigate on this case related to "index 0 out of bounds for length 0" error and get back to you soon once I have any finding. Meanwhile can I check with you on Quartus Version you are using? Windows/ Linux? For your solution: It is possible that you may have not implemented the Toolkit settings properly. I suggest you check your setup with an example design -> You can also get the eye opening. Thanks for your patience. Best regards, Harsh M2.1KViews0likes0Comments