Forum Discussion

Balkesh's avatar
Balkesh
Icon for New Contributor rankNew Contributor
1 year ago

Support Logic Generation Error

Hi,

I have got a error while executing a programm in Quatus prime pro software v23.1 the device i use to run the project was agib023r18a1e1v. If i execute the same module by making top then didn't got the error while some critical warning i got

Critical Warning(23469): The block i_etile_wrapper|av_top|eth_f_0|eth_f_0|hip_inst|per_xcvr[2].x_bb_f_ux|x_bb_f_ux_tx did not set the following parameters
Info(23470): Parameter txeq_main_tap
Info(23470): Parameter txeq_post_tap_1
Info(23470): Parameter txeq_pre_tap_1
Info(23470): Parameter txeq_pre_tap_2

Critical Warning(23469): The block i_etile_wrapper|av_top|eth_f_0|eth_f_0|hip_inst|per_xcvr[2].x_bb_f_ux|x_bb_f_ux_rx did not set the following parameters
Info(23470): Parameter rx_ac_couple_enable
Info(23470): Parameter rx_onchip_termination
Info(23470): Parameter rxeq_dfe_data_tap_1
Info(23470): Parameter rxeq_hf_boost
Info(23470): Parameter rxeq_vga_gain
Info(23470): Parameter vsr_mode


and when i make top to the main module i got this error

Error(22241): Cannot place the block i_etile_wrapper|av_top|eth_f_0|eth_f_0|hip_inst|per_xcvr[0].x_bb_f_ux|x_bb_f_ux_rx at location fgt_q0_ch0_rx because it uses port next_bonding_link that is not present at this location.

Error(22658): Cannot place block i_etile_wrapper|av_top|eth_f_0|eth_f_0|hip_inst|per_xcvr[0].x_bb_f_ux|x_bb_f_ux_rx in location fgt_q0_ch0_rx because it makes the block i_etile_wrapper|av_top|eth_f_0|eth_f_0|hip_inst|per_xcvr[1].x_bb_f_ux|x_bb_f_ux_rx unplaceable

In the project i want to change the e-tile 100gbe with f-tile 100gbe4

and r-tile pcie gen4x16 instead of p-tile how should i proceed.

please help

regards
Balkesh

Hdl

4 Replies

  • Harshx's avatar
    Harshx
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hi,

    Thanks for contacting Intel. I'm assigned to support request.

    I'll investigate on this case and get back to you soon once I have any finding.

    Meanwhile can I check with you on

    1. Please share the IP names you are using in your design.
    2. Is it possible for you to share archived design? If yes, kindly attach.

    Thanks for your patience.

    Best regards,

    Harsh M


    • Beginner_in_FPGA's avatar
      Beginner_in_FPGA
      Icon for Contributor rankContributor
      1 year ago

      Hi @Harshx ,


      I too am facing the same issue when using an F-Tile for the device AGI027R31B1E1V and Quartus 24.1 Prime Pro. Design in question is the Intel OFS F-Tile Design which I am porting to my own custom board.

      I have changed the Ethernet Subsystem to a single port 400GCAUI-4 using the 4 FHT Channels in one F-Tile and am using my own constraints. When compiling the same error pops up.

      Error(22241): Cannot place the block hssi_wrapper|hssi_ss|hssi_ss|U_eth_f_inst_p16|eth_f_top_p16|hip_inst|per_xcvr[0].x_bb_f_bk at location fht_ch0 because it uses port next_bonding_link that is not present at this location.

      Any updates on this case? It would be greatly helpful.

      Thank you,
      Best Regards.

  • Harshx's avatar
    Harshx
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hi,
    Apologies for delayed response.
    Is that possible for you to share your archived design? (Or related design so that issue can be replicated), If Yes kindly attach it.
    Thank you
    Regards,
    Harsh M