Stuck on the error: Verilog HDL Defparam Statement error at <location>: value for parameter "<name>" must be constant expression

Hi,

I'm trying to support the synthesis of my system on both Vivado and Quartus. So far i've had tough luck with Quartus (probably due to my inexperience).

I have a package in which i have some functions which set up my local parameters in other RTL files. The functions look like:

function automatic int get_settings_loading_serialised_width( );
 
      int settings_loading_serialised_width =   `REG_STATUS_FLAG_WIDTH +
 
                                                `REG_K_WIDTH +
 
                                                `L_C_WIDTH +
 
                                                `L_A_WIDTH +
 
                                                get_u_width() +
 
                                                `REG_ID_WIDTH +
 
                                                `L_E_REG_QM_WIDTH +
 
                                                15 +
 
                                                `REG_N_WIDTH + 
 
                                                $clog2(41+1) + 
 
                                                $clog2(211) +
 
                                                `REG_NU_WIDTH;
 
      return settings_loading_serialised_width;
 
  endfunction

There are some additions from the macros included within the package (eg: `REG_N_WIDTH )and some additions from the functions within the package (eg: get_u_width()). I then import this package within my top level module as localparam GET_SETTINGS: get_settings_loading_serialised_width( ) but i get the error: Verilog HDL Defparam Statement error at <location>:. Vivado does not have a problem with this.

P.S. I found that doing something like int a; a = `something; return a; works fine as compared to when int a = `something; return a;

Can anyone please help me with this?

Regards.