Stuck on the error: Verilog HDL Defparam Statement error at <location>: value for parameter "<name>" must be constant expression

I am using Quartus Prime 18.1 (standard). I've found the problem. Apparently for Quartus, having a declaration and initialization on the same line (e.g int a = 10 -> Quartus treats this as a non-constant expression) is different from having a separate line for variable declaration and initalization (int a; a = 10; ->Quartus apparently likes this). This is very bizarre. I don't fully understand why this is the case.