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AKhan88's avatar
AKhan88
Icon for New Contributor rankNew Contributor
6 years ago

Stuck on the error: Verilog HDL Defparam Statement error at <location>: value for parameter "<name>" must be constant expression

Hi, I'm trying to support the synthesis of my system on both Vivado and Quartus. So far i've had tough luck with Quartus (probably due to my inexperience). I have a package in which i have some fun...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

I cannot reproduce the error in your previous reply. Using int in the verilog file caused a syntax error. Could you provide the qar file for investigation?

Thanks.

Best regards,

KhaiY

  • AKhan88's avatar
    AKhan88
    Icon for New Contributor rankNew Contributor
    6 years ago

    It's against my company policy to do so. Apologies for that.

    If you really want to recreate it. Try doing what i did in the question i asked above. That function is inside a package and is imported within a module. Try compiling it in Quartus that way.